1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device and a method for fabricating the same, to minimize the signal distortion by decreasing the instability of voltage in a—Si:H TFT of a gate driving signal output unit.
2. Discussion of the Related Art
Demands for various display devices have increased with the growth and popularity of information technology. Accordingly, many efforts have been made to research and develop various flat display devices such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD). Some species of flat display devices have already been applied to displays for various
Among the various flat display devices, liquid crystal display (LCD) devices have been the most widely used due to their advantageous characteristics such as thin profile, light weight, and low power consumption, to the point where LCD devices are a substitute for Cathode Ray Tubes (CRTs). In addition to mobile type LCD devices such as those in notebook computers, LCD devices have been developed for computer monitors and televisions receiving and displaying broadcasting signals.
Hereinafter, a related art LCD device will be described with reference to the accompanying drawings.
FIG. 1 illustrates a layout of a related art LCD device. As illustrated in FIG. 1, the related art LCD device includes an LCD panel 20, a gate driving unit 12, a data driving unit, and a timing controller 16. The LCD panel 20 includes lower and upper substrates 11 and 10, and a liquid crystal layer (not illustrated) formed between the lower and upper substrates. The gate driving unit 12 includes a plurality of gate drivers (12_1, 12_2, . . . , 12_n), wherein the plurality of gate drivers are formed on the predetermined portion of the lower substrate 11. Also, the data driving unit 15 includes a plurality of data drivers (15_1, 15_2, . . . , 15_m), wherein the plurality of data drivers are connected with a source PCB 14 by a data TCP 13. The timing controller 16 outputs control signals and video data to the gate driving unit 12 and the data driving unit 15.
In addition, a plurality of control signal lines are provided so as to provide the control signals outputted from the timing controller 16 to a gate drive IC 12. The timing controller 16 controls the driving timing of the gate driving unit 12 and the data driving unit 15 with a predetermined clock signal CLK, a gate start signal, and a timing signal.
A plurality of input signal lines are connected with the respective control signal lines, wherein the signals are inputted to the respective gate drivers (12_1, 12_2, . . . , 12_n) of the gate driving unit 12 by the input signal lines. Although not illustrated, scanning signals are sequentially outputted to respective gate pads of the lower substrate 11 by the output signal lines of the gate driving unit 12.
In the LCD panel 20, a pixel unit 8 is defined to display the image. Although not illustrated, the lower substrate 11 includes a plurality of gate lines G/L, a plurality of data lines D/L, a plurality of pixel electrodes, and a plurality of thin film transistors TFT. The plurality of gate lines G/L intersect the respective data lines D/L at the right angles, thereby defining a plurality of pixel regions. The plurality of pixel electrodes are respectively formed in the pixel regions defined by the gate lines G/L and the data lines D/L. Also, the plurality of thin film transistors TFTs are formed at the respective intersection points of the gate and data lines, wherein the signals of the data lines D/L are applied to the respective pixel electrodes according to the signals of the gate lines G/L.
The thin film transistor TFT includes a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode. The gate electrode is protruding from one side of the gate line. The gate insulating layer is formed on an entire surface of the lower substrate 11 including the gate electrode. The active layer is overlapped with the gate electrode. Then, the source electrode is overlapped with one side of the data line and one side of the gate electrode. The drain electrode is formed at the predetermined interval from the source electrode. In addition, an ohmic contact layer is formed between the active layer and the source and drain electrodes. Then, a passivation layer is formed on the entire surface of the substrate including the data line, wherein the passivation layer has a first contact hole in the drain electrode. In this state, the drain electrode is in contact with the pixel electrode by the first contact hole.
Although not illustrated, the upper substrate 10 includes a black matrix layer, a color filter layer and a common electrode. The color filter is coated on the upper substrate 10, wherein the color filter is formed in state of being divided in correspondence with the pixel regions of the lower substrate 11 by the black matrix layer. The common electrode corresponds to the pixel electrode of the lower substrate 11.
According as turn-on signals are sequentially applied to the gate lines, the data signal is applied to the pixel electrode of the corresponding line, thereby displaying the image.
Although not illustrated, the gate driving unit 12 and the data driving unit 15 are formed of a plurality of buffer TFTs. Especially, the buffer TFT of the gate driving unit 12 is formed of a—Si:H TFT.
Hereinafter, a related art gate driving unit having a buffer TFT of a—Si:H TFT will be described with reference to the accompanying drawings.
FIG. 2 is a circuit view of a gate driving unit according to one type of the related art. FIG. 3A is a plane view of a pull-up transistor PU in ‘A’ area of FIG. 2. FIG. 3B is a cross sectional view of a pull-up transistor PU in ‘A’ area of FIG. 2. FIG. 4 is an output wave form of explaining the problems of a related art gate driving unit. FIG. 5 is a circuit view of a gate driving unit according to another type of the related art. FIG. 6 is a cross sectional view of a pull-up transistor PU and a capacitor C1 of FIG. 5.
As illustrated in FIG. 2, the related art gate driving unit includes a signal controller 21, and a gate driving signal output unit. The signal controller 21 outputs first and second control signals Q and /Q. The gate driving signal output unit receives the first and second control signals Q and /Q from the signal controller 21, and then outputs the gate signal to the gate line G/L of the pixel unit.
The gate driving signal output unit includes a pull-up transistor PU and a pull-down transistor PD of a—Si:H TFT, wherein the gate driving signal output unit is provided between a clock signal terminal CLK and a ground voltage terminal VSS. The gate driving signal is outputted through an output node 1 N1 between the pull-up transistor PU and the pull-down transistor PD. The pull-up transistor and the pull-down transistor may be turned on and off according to the first and second control signals Q and /Q. The gate driving signal is outputted with the charge of the pull-up transistor and the discharge of the pull-down transistor.
In the aforementioned gate driving signal output unit, the clock signal CLK is applied to one end of the pull-up transistor. In the pull-up transistor, as illustrated in FIG. 3A and FIG. 3B, a gate electrode 31 is formed on the predetermined portion of a substrate 30, and a gate insulating layer 32 is formed on an entire surface of the substrate 30 including the gate electrode 31. Also, an active layer 33 is formed on the gate insulating layer 32 above the gate electrode 31. Then, source and drain electrodes 35a and 35b are formed at both sides of the active layer 33. The overlapped area L1 between the source electrode 35a and the gate electrode 31 is same as the overlapped area L2 between the drain electrode 35b and the gate
In addition, an ohmic contact layer 34 is formed between the active layer 33 and the source and drain electrodes 35a and 35b. The active layer 33 is formed of an amorphous silicon layer, and the ohmic contact layer 34 is formed of an n-type amorphous silicon layer.
In this state, the clock signal CLK is applied to the source electrode 35a of the pull-up transistor PU. When the clock signal CLK is periodically applied to the source electrode of the pull-up transistor PU, and the gate electrode of the pull-up transistor PU and the pull-down transistor PD connected with the gate signal output terminal is in the floating state, the first and second control signals Q and /Q are unstable since the clock signal CLK is applied to the source electrode 35a of the pull-up transistor PU. Accordingly, as illustrated in FIG. 4, it may cause an abnormal gate output signal GL which is not synchronized with the first and second control signals Q and /Q.
This is not a significant problem in the initial drive of the gate driving circuit. However, if the pull-up transistor is discharged due to a heated LCD panel, the plurality of gate driving signals are outputted by the clock signal CLK, thereby causing flickering, degrading the picture quality. That is, as illustrated in FIG. 4, on applying the input signal of the first and second control signals Q and /Q, the abnormal gate driving signal is outputted due to the raise of the voltage in the second control signal /Q of the pull-down transistor PD.
Accordingly, in order to solve these problems, as illustrated in FIG. 5 and FIG. 6, a capacitor C1 is additionally provided between the source electrode and the gate electrode of the pull-up transistor PU. That is, as illustrated in FIG. 6, a gate electrode 61 is formed on the predetermined portion of a substrate 60, and a first conductive layer 61a is formed on the same layer as the gate electrode 61. Then, a gate insulating layer 62 is formed on the gate electrode 61 and the first conductive layer 61a. In addition, an active layer 63 is formed on the gate insulating layer 62 above the gate electrode 61. Furthermore, source and drain electrode 64a and 64b are formed at both sides of the active layer 63, wherein the source and drain electrode 64a and 64b are partially overlapped with the gate electrode 61. The drain electrode 64b is formed above the first conductive layer 61a. 
After that, an insulating interlayer 65 is formed on the entire surface of the substrate 60 including the source and drain electrodes 64a and 64b. In this case, first and second contact holes are formed to expose the drain electrode 64b above the active layer 64 and the conductive layer 61a. Then, a second conductive layer 66 is formed on the insulating interlayer 65, wherein the second conductive layer 66 is in contact with the drain electrode 64b through the first and second contact holes. Also, an ohmic contact layer 63a is formed between the active layer 63 and the source and drain electrodes 64a and 64b. 
In this case, the first conductive layer 61a is extended from the gate electrode 61, wherein the first conductive layer 61 functions as a lower capacitor electrode. Also, the second conductive layer 66 is in contact with the drain electrode 64b through the second contact hole, wherein the second conductive layer 66 functions as an upper capacitor electrode. Thus, the capacitor C1 is additionally formed between each of the first conductive layer 61a, the gate insulating layer 61 and the drain electrode 64b. 
However, if the additional capacitor C1 is formed between the source electrode and the gate electrode of the pull-up transistor PU, the size of device increases, so that the integration of device is lowered.